The present invention relates generally to digital circuits. More particularly, the present invention relates to a digital frequency doubler circuit that compensates for practical variations in manufacturing processes and operating conditions.
Many digital circuits utilize a frequency doubler that doubles the rate of a digital clock signal. Digital frequency doublers may utilize delay elements designed to delay a digital signal by either an absolute amount or by a defined fraction of its clock period. For example, if a clock signal with a period of 3.2 nanoseconds needs to be frequency doubled, the clock signal can be buffered to generate a delay of 800 picoseconds, then the original clock signal and the delayed clock signal can be subjected to an XOR operation, thus creating a waveform with a period of 1600 picoseconds and a high time of 800 picoseconds. In this regard, the original clock signal should be delayed with an appropriate number of buffers to arrive at a nominal delay of 800 picoseconds. In real world applications, however, variations in process, temperature, voltage, and other environmental conditions can result in an actual delay that ranges between 500 picoseconds to 1100 picoseconds. This would result in an output clock signal having a duty cycle within the range of 31% to 69%, rather than the desired 50% duty cycle.
One known solution to the above problem is to design the downstream circuitry to accommodate the worst case duty cycle. For example, a practical application may utilize relatively high powered flip flop devices that are capable of tolerating a wider range in clock signal duty cycle. Unfortunately, this solution results in an inefficient, riskier, and higher powered design.
Another prior art approach utilizes a high speed shift register to delay an external clock signal. This solution typically requires a relatively high amount of operating power, and it introduces the problem of metastability (the metastability issue can be addressed at the expense of additional operating power).
Accordingly, it would be desirable to have a digital frequency doubling circuit that generates a frequency doubled clock signal having a relatively narrow range of duty cycles across a variety of process and/or environmental conditions.
A digital frequency doubling circuit according to the present invention compensates for variations in process and environmental conditions by using a stable reference clock signal and two matched delay line elements. The frequency doubling circuit is capable of generating a frequency doubled clock signal having a nominal duty cycle and within narrow tolerances relative to conventional frequency doubling circuits.
The above and other aspects of the present invention may be carried out in one form by a method for altering the frequency of a digital clock signal. The method involves: applying a reference clock signal to a reference delay element; applying an input clock signal to an input delay element, where the reference delay element and said input delay element having matching operational characteristics; obtaining, from the reference delay element, information identifying delay characteristics of the reference delay element; generating a delayed clock signal, based upon the input clock signal, in response to the information; and deriving an output clock signal from the delayed clock signal and the input clock signal. The derived output clock signal has a higher frequency than said input clock signal.